View AK4524VM_4089576.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

[ak4524] m0050-e-04 2012/01 - 1 - general description the ak4524 is a high performance 24bit codec for the 96khz recording sy stem. the adc has an enhanced dual bit architecture with wide dynamic range. the dac uses the new developed advanced multi bit architecture and achieves low outband noise and high jitter tolerance by use of scf (switched capacitor filter) techniques. t he ak4524 has an input pga and is we ll-suited md, dvtr system and musical instruments. features ? 24bit 2ch adc - 64x oversampling - single-end inputs - s/(n+d): 90db - dynamic range, s/n: 100db - digital hpf for offset cancellation - input pga with +18db gain & 0.5db step - input datt with -72db att - i/f format: msb justified or i 2 s ? 24bit 2ch dac - 128x oversampling - 24bit 8 times digital filter ripple: 0.005db, attenuation: 75db - scf - differential outputs - s/(n+d): 94db - dynamic range, s/n: 110db - de-emphasis for 32kh z, 44.1khz, 48khz sampling - output datt with -72db att - soft mute - i/f format: msb justified, lsb justified or i 2 s ? high jitter tolerance ? 3-wire serial interface for volume control ? master clock - x?tal oscillating circuit - 256fs/384fs/512fs/768fs/1024fs ? master mode/slave mode ? 5v operation ? 3v power supply pin for 3v i/f ? small 28pin ssop package 24bit 96khz audio codec ak4524
[ak4524] m0050-e-04 2012/01 - 2 - ? block diagram a inl a inr vcom a outl+ a outl- a outr- a outr+ vref va a gnd cs cclk cdti cif clko xto xti xtale sdti sdto bick lrck dgnd vt vd a dc dac hpf datt datt smute a udio i/f controller control register i/f clock gen. & divider pd m/ s block diagram
[ak4524] m0050-e-04 2012/01 - 3 - ? ordering guide AK4524VM 20 a +85 q c 28pin ssop (0.65mm pitch) ? pin layout (internal pull down) test vcom ainr ainl vref agnd va xto xti xtale lrck bick sdto sdti cdti cclk cs cif clko vt vd dgnd aoutl- aoutl+ aoutr- aoutr+ pd m/ s 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 ak4524 top view
[ak4524] m0050-e-04 2012/01 - 4 - pin/function no. pin name i/o function 1 vcom o common voltage output pin, va/2 bias voltage of adc inputs and dac outputs. 2 ainr i rch analog input pin 3 ainl i lch analog input pin 4 vref i voltage reference input pin, va used as a voltage reference by adc & dac. vref is connected externally to filtered va. 5 agnd - analog ground pin 6 va - analog power supply pin, 4.75 5.25v 7 test i test pin (internal pull-down pin) 8 xto o x?tal output pin 9 xti i x?tal/master clock input pin 10 xtale i x?tal osc enable pin ?h?: enable, ?l?: disable 11 lrck i/o input/output channel clock pin 12 bick i/o audio serial data clock pin 13 sdto o audio serial data output pin 14 sdti i audio serial data input pin 15 cdti i control data input pin 16 cclk i control data clock pin 17 cs i chip select pin 18 cif i control data i/f format pin ?h?: cs falling trigger, ?l?: cs rising trigger 19 pd i power-down mode pin ?h?: power up, ?l?: power down, reset and initialize the control register. 20 m/ s i master/slave mode pin ?h?: master mode, ?l?: slave mode 21 clko o master clock output pin 22 vt - output buffer power supply pin, 2.7 5.25v 23 vd - digital power supply pin, 4.75 5.25v 24 dgnd - digital ground pin 25 aoutl ? o lch negative analog output pin 26 aoutl+ o lch positive analog output pin 27 aoutr ? o rch negative analog output pin 28 aoutr+ o rch positive analog output pin note: all input pins except pull-down pins should not be left floating.
[ak4524] m0050-e-04 2012/01 - 5 - absolute maximum ratings (agnd, dgnd=0v; note 1) parameter symbol min max unit power supplies: analog digital output buffer vd ? va va vd vt vda ? 0.3 ? 0.3 ? 0.3 - 6.0 6.0 6.0 0.3 v v v v input current, any pin except supplies iin - 10 ma analog input voltage vina ? 0.3 va+0.3 v digital input voltage vind ? 0.3 va+0.3 v ambient temperature (powered applied) ta ? 20 85 c storage temperature tstg ? 65 150 c note: 1. all voltages with respect to ground. warning: operation at or beyond these limits may result in permanent damage to the device. normal operation is not guaranteed at these extremes. recommended operating conditions (agnd, dgnd=0v; note 1) parameter symbol min typ max unit power supplies (note 2) analog digital output buffer va vd vt 4.75 4.75 2.7 5.0 5.0 3.0 5.25 va vd v v v voltage reference vref 3.0 - va v note: 1. all voltages with respect to ground. 2. va and vd should be powered at the same time or va should be powered earlier than vd. the power up sequence between va and vt, or vd and vt is not critical. *akm assumes no responsibility for the usage beyond the conditions in this datasheet.
[ak4524] m0050-e-04 2012/01 - 6 - analog characteristics (ta=25 c; va, vd, vt=5.0v; agnd=dgnd=0v; vref=va; fs =44.1khz; signal frequency=1khz; 24bit data; measurement frequency = 10hz 20khz at fs=44.1khz, 10hz 40khz at fs=96khz; unless otherwise specified) parameter min typ max unit input pga characteristics: input voltage (note 3) 2.7 2.9 3.1 vpp input resistance 5 10 15 k step size 0.2 0.5 0.8 db gain control range 0 18 db adc analog input characteristics: ipga=0db resolution 24 bits s/(n+d) ( ? 0.5dbfs) fs=44.1khz fs=96khz 84 80 90 88 db db dr ( ? 60dbfs) fs=44.1khz, a-weighted fs=96khz 94 88 100 96 db db s/n fs=44.1khz, a-weighted fs=96khz 94 88 100 96 db db interchannel isolation 90 105 db interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c power supply rejection (note 4) 50 - db dac analog output characteristics: resolution 24 bits s/(n+d) (0dbfs) fs=44.1khz fs=96khz 88 85 94 93 db db dr ( ? 60dbfs) fs=44.1khz, a-weighted fs=96khz 104 96 110 104 db db s/n fs=44.1khz, a-weighted fs=96khz 104 96 110 104 db db interchannel isolation 100 110 db interchannel gain mismatch 0.2 0.5 db gain drift 20 - ppm/ c output voltage (note 5) 5.0 5.4 5.8 vpp load resistance (in case of ac load) 1 k output current (in case of ac load) 1.5 ma load capacitance 25 pf note: 3. full scale (0db) of the input voltage at pga=0db. this voltage is proportional to vref. vin=0.58 x vref. 4. psr is applied to va, vd, vt with 1khz, 50mvpp. vref pin is held a constant voltage. 5. full scale (0db) of the output volta ge when summing the differential outputs, aout+/ ? by unity gain. this voltage is proportional to vref. vout=1.08 x vref x gain.
[ak4524] m0050-e-04 2012/01 - 7 - parameter min typ max unit power supplies power supply current normal operation ( pd = ?h?) va vd+vt (fs=44.1khz) (fs=96khz) power-down mode ( pd = ?l?) (note 6) va vd+vt 30 16 24 10 10 45 24 36 100 100 ma ma ma a a note: 6. xtale=?l? and all digital input pins are held vd or dgnd. filter characteristics (ta=25 c; va, vd=4.75 5.25v; vt=2.7 5.25v; fs=44.1khz; dem=off) parameter symbol min typ max unit adc digital filter (decimation lpf): passband (note 7) ? 0.005db ? 0.02db ? 0.06db ? 6.0db pb 0 - - - 20.02 20.20 22.05 19.76 - - - khz khz khz khz stopband sb 24.34 khz passband ripple pr 0.005 db stopband attenuation sa 80 db group delay (note 8) gd 31 1/fs group delay distortion gd 0 s adc digital filter (hpf): frequency response (note 7) ? 3db ? 0.5db ? 0.1db fr 0.9 2.7 6.0 hz hz hz dac digital filter: passband (note 7) ? 0.01db ? 6.0db pb 0 - 22.05 20.0 - khz khz stopband sb 24.1 khz passband ripple pr 0.005 db stopband attenuation sa 75 db group delay (note 8) gd 30 1/fs dac digital filter + scf: frequency response: 0 20.0khz 40khz (note 9) fr 0.2 0.3 db db note: 7. the passband and stopband frequencies scale with fs. for example, 20.02khz at ? 0.02db is 0.454 x fs. the reference frequency of these responses is 1khz. 8. the calculating delay time which occurred by di gital filtering. this time is from the input of analog signal to setting the 24bit data of both channels to the output register for adc. for dac, this time is from setting the 24bit data of both channels on input register to the output of analog signal. 9. fs=96khz.
[ak4524] m0050-e-04 2012/01 - 8 - digital characteristics (ta=25 c; va, vd=4.75 5.25v; vt=2.7 5.25v) parameter symbol min typ max unit high-level input voltage low-level input voltage vih vil 2.2 - - - - 0.8 v v high-level output voltage (iout= ? 100 a) (note 10) low-level output voltage (iout=100 a) voh vol 2.7 / vt ? 0.5 - - - - 0.5 v v input leakage current iin - - 10 a note: 10. min value is lower voltage of 2.7v or vt ? 0.5v. switching characteristics (ta=25 c; va, vd=4.75 5.25v, vt=2.7 5.25v; c l =20pf) parameter symbol min typ max unit master clock timing crystal resonator frequency 11.2896 24.576 mhz external clock frequency pulse width low pulse width high fclk tclkl tclkh 8.192 0.4/fclk 0.4/fclk 49.152 mhz ns ns clko output (x?tal mode) frequency duty cycle fmck dmck 11.2896 35 24.576 65 mhz % lrck frequency normal speed mode (dfs0=?0?, dfs1=?0?) double speed mode (dfs0=?1?, dfs1=?0?) quad speed mode (dfs0=?0?, dfs1=?1?) fsn fsd fsq 32 64 128 48 96 192 khz khz khz duty cycle slave mode master mode 45 50 55 % % audio interface timing slave mode bick period bick pulse width low pulse width high lrck edge to bick ? ? (note 11) bick ? ? to lrck edge (note 11) lrck to sdto (msb) (except i 2 s mode) bick ? ? to sdto sdti hold time sdti setup time tbck tbckl tbckh tlrb tblr tlrs tbsd tsdh tsds 81 33 33 20 20 20 20 40 40 ns ns ns ns ns ns ns ns ns master mode bick frequency bick duty bick ? ? to lrck bick ? ? to sdto sdti hold time sdti setup time fbck dbck tmblr tbsd tsdh tsds -20 -20 20 20 64fs 50 20 20 hz % ns ns ns ns note 11. bick rising edge must not occur at the same time as lrck edge.
[ak4524] m0050-e-04 2012/01 - 9 - parameter symbol min typ max unit control interface timing cif=?0? cclk period cclk pulse width low pulse width high cdti setup time cdti hold time cs ?h? time cs ?l? time cs ? ? to cclk ? ? cclk ? ? to cs ? ? tcck tcckl tcckh tcds tcdh tcsw tcsw tcss tcsh 200 80 80 40 40 150 150 150 50 ns ns ns ns ns ns ns ns ns cif=?1? cclk period cclk pulse width low pulse width high cdti setup time cdti hold time cs ?h? time cs ?l? time cs ? ? to cclk ? ? cclk ? ? to cs ? ? tcck tcckl tcckh tcds tcdh tcsw tcsw tcss tcsh 200 80 80 40 40 150 150 150 50 ns ns ns ns ns ns ns ns ns reset timing pd pulse width (note 12) rstad ? ? to sdto valid (note 13) tpd tpdv 150 516 ns 1/fs note: 12. the ak4524 can be reset by bringing pd ?l?. 13. these cycles are the number of lrck rising from rstad bit.
[ak4524] m0050-e-04 2012/01 - 10 - ? timing diagram 1/fclk tclkl vih tclkh mclk vil 1/fs lrck vih vil tbck tbckl vih tbckh bick vil tl 50%vt th clko dmck=th/(th+tl) or tl/(th+tl) clock timing lrck bick sdto sdti tblr tlrb tlrs tbsd tsds tsdh vih vil vih vil 50%vt vih vil audio interface timing (slave mode)
[ak4524] m0050-e-04 2012/01 - 11 - lrck bick sdto sdti tmblr tbsd tsds tsdh 50%vt vih vil 50%vt 50%vt audio interface timing (master mode) cs(cif=h) cs(cif=l) cclk cdti vih vil tcss tcckl tcckh tcds tcdh c1 c0 r/w a 4 vih vil vih vil vih vil write command input timing cs(cif=h) cs(cif=l) cclk cdti tcsw tcsh vih vil d3 d2 d1 d0 vih vil vih vil vih vil write data input timing tpd vil pd power down & reset timing
[ak4524] m0050-e-04 2012/01 - 12 - operation overview ? system clock input the master clock (mclk) can be either a crystal resonator pl aced across the xti and xto pin, or external clock input to the xti pin with the xto pin left floating. the master cl ock frequency can be selected by cmode and cks0-1 (table 1). the sampling speed (normal speed mode, double speed mode or four times speed monitor mode) is selected by dfs0-1 (table 2). the adc is powered down during four times speed monitor mode. the frequency of the master clock output (clko) is the same as mclk frequency and the output can be enabled or disabled by xtale pin. when the clko output is not used externally, it should be disabled. when using a crystal oscillator, external loading capacitors (between xti/xt o and dgnd) are required. in slave mode, the lrck clock input must be synchronized with mclk, however th e phase is not critical. internal timing is synchronized to lrck upon power-up. all external clocks must be present unless pd =?l? or all parts are powered down by control register, otherwise excessive current may re sult from abnormal operation of internal dynamic logic. in master mode, the clocks should be supp lied by critical oscillation except for power down or the external clock (mclk) should not be stopped. dfs1 dfs0 sampling rate monitor mode 0 0 normal speed - 0 1 double speed - 1 0 4 times speed (sdto = ?l?) simple decimation 1 1 4 times speed (sdto = ?l?) 2 tap filter at reset table 1. sampling speed mclk cmode cks1 cks0 normal speed (dfs1-0 = ?00?) double speed (dfs1-0 = ?01?) 4 times speed (dfs1-0 = ?10? or ?11?) 0 0 0 256fs n/a n/a 0 0 1 512fs 256fs 128fs 0 1 0 1024fs 512fs 256fs 1 0 0 384fs n/a n/a 1 0 1 768fs 384fs 192fs at reset table 2. master clock frequency select
[ak4524] m0050-e-04 2012/01 - 13 - mclk(normal speed) fs=44.1khz fs=48khz mclk(double speed) fs=88.2khz fs=96khz 256fs 11.2896mhz 12.288mhz n/a n/a n/a 512fs 22.5792mhz 24.576mhz 256fs 22.5792mhz 24.576mhz 1024fs 45.1584mhz 49.152mhz 512fs 45.1584mhz 49.152mhz 384fs 16.9344mhz 18.432mhz n/a n/a n/a 768fs 33.8688mhz 36.864mhz 384fs 33.8688mhz 36.864mhz mclk(4 times speed) fs=176.4khz fs=192khz 128fs 22.5792mhz 24.576mhz 256fs 45.1584mhz 49.152mhz 192fs 33.8688mhz 36.864mhz table 3. master clock frequency * x?tal mode operates from 11.2896mhz to 24.576mhz. * the frequency over 24.576mhz supports only external clock mode. ? audio serial interface format five serial modes selected by the dif0 and dif1 pins are s upported as shown in table 4. in all modes the serial data has msb first, 2?s compliment format. the sdto is clocked out on the falling edge of bick and the sdti is latched on the rising edge. the interface supports both ma ster mode and slave mode. in master mode, bick and lrck are outputs and the frequency of bick is fixed to 64fs. mode dif2 dif1 dif0 sdto sdti lrck bick 0 0 0 0 24bit, msb justified 16bit, lsb justified h/l t 32fs 1 0 0 1 24bit, msb justified 20bit, lsb justified h/l t 40fs 2 0 1 0 24bit, msb justified 24bit, msb justified h/l t 48fs 3 0 1 1 24bit, iis (i2s) 24bit, iis (i2s) l/h t 48fs 4 1 0 0 24bit, msb justified 24bit, lsb justified h/l t 48fs at reset table 4. audio data format lrck bick ( 64fs ) sdto(o) 012 19 17 18 20 31 0 1 2 19 17 18 20 31 0 23 1 22 4 23 22 7 6 4 23 sdti ( i ) 1 14 0 12 11 1 14 0 12 11 sdto-19:msb, 0:lsb; sdti-15:msb, 0:lsb lch data rch data don?t care don?t care 76 bick(32fs) sdto ( o ) 0 1 2 9 10 12 13 15 0 1 2 9 10 12 13 15 0 23 1 22 12 23 22 12 15 14 23 sdti(i) 1 60 43 1 15 0 54 15 14 2 98 11 10 21 15 14 13 31114 13 5 7 21 5 3 13 15 30 21 33 21 14 13 7 6 3 2 15 14 11 8 9 10 11 13 5 3 15 13 2 2 figure 1. mode 0 timing
[ak4524] m0050-e-04 2012/01 - 14 - lrck bick(64fs) sdto ( o ) 0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 23 1 22 0 23 22 12 11 10 0 23 sdti(i) 1 18 0 19 8 7 1 18 0 19 8 7 sdto-23:msb, 0:lsb; sdti-19:msb, 0:lsb lch data rch data don?t care don?t care 12 11 10 figure 2. mode 1 timing lrck bick(64fs) sdto ( o ) 0 1 2 1819202122 0 1 2 181920 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 54 10 32 10 32 23 figure 3. mode 2 timing lrck bick(64fs) sdto ( o ) 0 1 2 3 19 20 21 22 0 1 2 3 19 20 22 21 0 1 sdti(i) 23 24 25 23 24 25 23 22 4 23 22 5 4 5 4 1 22 0 23 3 2 1 22 0 23 3 2 23:msb, 0:lsb lch data rch data don?t care don?t care 5 54 10 32 10 32 figure 4. mode 3 timing lrck bick ( 64fs ) sdto ( o ) 0 1 2 8 9 10 20 21 31 0 1 2 8 9 10 20 21 31 0 23 1 22 0 23 22 16 15 14 0 23 sdti ( i ) 1 22 0 23 12 11 1 22 0 23 12 11 23:msb, 0:lsb lch data rch data don?t care don?t care 16 15 14 figure 5. mode 4 timing
[ak4524] m0050-e-04 2012/01 - 15 - ? input volume the ak4524 includes two channel independent analog volumes (ip ga) with 37 levels, 0.5db step in front of adc and digital volumes (iatt) with 128 levels (including mute) after adc. the control data of both volumes are assigned in the same register address. when msb of the register is ?1?, the ipga changes and the iatt changes at msb ?0?. the ipga is analog volumes and improves s/n compared with digital volume (table 5). level changes only occur during zero-crossings to minimize switching noise. zero-crossing det ection is performed channel independently. if there is no zero-crossings, then the level w ill change after a time-out. the time-out period (t o) scales with fs. the periods of 256/fs, 512/fs, 1024/fs and 2048/fs are se lectable by ztm1-0 bits in normal speed mode. if new value is written to the ipga register before ipga changes by zero-crossing or time-out, the previous value becomes invalid. and then the timer (channel independent) for time-out is rese t and the timer restarts for new ipga value. zero-crossing detection can be enabled by zcei in the control register. the iatt is a pseudo-log volume linear-int erpolated internally. when changing th e level, the transition between att values has 8032 levels and is done by soft change s. therefore, there is not any switching noise. input gain setting 0db +6db +18db fs=44.1khz, a-weight 100db 98db 90db table 5. ipga+adc s/n ztm1 ztm0 normal speed double speed 0 0 256 512 0 1 512 1024 1 0 1024 2048 1 1 2048 4096 at reset table 6. lrck cycles for timeout period ? digital high pass filter the adc has a digital high pass filter for dc offset cancel. the cut-off frequency of the hpf is 0.9hz at fs=44.1khz and also scales with sampling rate (fs). ? output volume the ak4524 includes digital volumes (oatt) with 128 levels (including mute) which have the same architecture as iatt?s in front of dac. t he oatt is a pseudo-log volume linear-interpolated internally. when changing the level, the transition between att values has 8032 levels and is done by soft changes. therefore, there is not any switching noise.
[ak4524] m0050-e-04 2012/01 - 16 - ? de-emphasis filter the dac includes the digital de-emphasis filter (tc=50/15 p s) by iir filter. this filter corresponds to three frequencies (32khz, 44.1khz, 48khz). this setting is done via contorl register. this filter is always off at double speed and four times speed modes. no dem1 dem0 mode 0 0 0 44.1khz 1 0 1 off 2 1 0 48khz 3 1 1 32khz at reset table 7. de-emphasis control (dfs0=dfs1=?0?) ? soft mute operation soft mute operation is performed at digital domain. when smute goes ?h?, the output signal is attenuated by f during 1024 lrck cycles. when smute is returned to ?l?, the mu te is cancelled and the output attenuation gradually changes to 0db during 1024 lrck cycles. if the soft mute is cancelled within 1024 lrck cycles after starting the operation, the attenuation is discontinued and returned to 0db. the soft mu te is effective for changing the signal source without stopping the signal transmission. soft mute function is independent to output vol ume and cascade connected between both functions. smute a ttenuation 1024/fs 0db - f 1024/fs gd gd (1) (2) (3) figure 6. soft mute notes: (1) the output signal is attenuated by f during 1024 lrck cycles (1024/fs). (2) analog output corresponding to digital input has the group delay (gd). (3) if the soft mute is cancelled within 1024 lrck cycles, the attenuation is discontinued and returned to 0db.
[ak4524] m0050-e-04 2012/01 - 17 - ? power down & reset the adc and dac of ak4524 are placed in the powe r-down mode by bringi ng a power down pin, pd ?l? and each digital filter is also reset at the same time. the internal register values are initialized by pd ?l?. this reset should always be done after power-up. and then as both control registers of adc and dac go reset state (rstad=rstda=?0?), each register sholud be cancelled after doing the needed se tting. in case of the adc, an analog initialization cycle starts after exiting the power-down or reset state. therefore, the output data, sdto becomes available after 516 cycles of lrck clock. this initialization cycle does not affect the dac operation. power down mode can be also controlled by the registers (pwad, pwda). power supply rstad(register) rstda(register) pwad(register) pwda(register) pwvr(register) a dc internal state iatt sdto oatt a out dac internal state external mute example external clocks in slave mode the clocks can be stopped. pd reset inita normal pd inita normal 00h 00h o xxh xxh 00h 00h o xxh xxh ?0? ?0? fi output fi output pd reset pd normal normal 00h 00h o xxh xxh 00h 00h o xxh xxh ?0? ?0? fi output fi mclk, lrck, bick pd pin ** * * x inita: initializing period of adc analog section (516/fs). x pd: power down state. the contents of all registers are hold. x xxh: the current value in att register. x fi: fade in. after exiting power down and reset state, att value fades in. x aout: some pop noise may occur at ?*?. figure 7. reset & power down sequence
[ak4524] m0050-e-04 2012/01 - 18 - ? relationship between clock operation and power-down xtale pin controls the clock outputs. the operation in slave mode is shown table 8. table 9 shows the master mode operation. when a crystal oscillator is used, xtale pin is se t to ?h?. xtale pin should be ?l? at external clock mode. xtale=l xtale=h slave mode pd =h pd =l pd =h pd =l xtal mode inhibit inhibit normal operation xtal = oscillation clko = output lrck = input bick = input power down xtal = oscillation clko = output lrck = input bick = input ext clock mode normal operation xti = mclk in xto = l clko = l lrck = input bick = input shut off xti = mclk in xto = l clko = l lrck = input bick = input inhibit inhibit table 8. clock operation at slave mode (m/ s = l) xtale=l xtale=h master mode pd =h pd =l pd =h pd =l xtal mode inhibit inhibit normal operation xtal = oscillation clko = output lrck = output bick = output power down xtal = oscillation clko = output lrck = h bick = l ext clock mode normal operation xti = mclk in xto = l clko = l lrck = output bick = output shut off xti = mclk in xto = l clko = l lrck = h bick = l inhibit inhibit table 9. clock operation at master mode (m/ s = h)
[ak4524] m0050-e-04 2012/01 - 19 - ? serial control interface the internal registers are written by the 3-wire p p interface pins: cs, cclk, cdti. the data on this interface consists of chip address (2bits, c0/1) read/write (1bit), register addre ss (msb first, 5bits) and contro l data (msb first, 8bits). address and data is clocked in on the rising edge of cclk. data is latched after the 16th rising edge of cclk, after a high-to-low transition of cs. the operation of the control serial port may be completely asynchronous with the audio sample rate. the maximum clock speed of the cclk is 5m hz. the cs should be ?h? or ?l? if no access. the chip address is fixed to ?10?. writing is invalid for the access to the chip a ddress except for ?10?. pd = ?l? resets the registers to their default values. cs (cif=0) cclk 01 2 345 67891011 12 13 14 15 cdti c1 c0 a 2 a 3 a 1 a 0 a 4 d7d6d5d4d3d2d1d0 r/w c1-c0: chip address (fixed to ?10?) r/w: read/write (fixed to ?1?:write) a 4-a0: register address d7-d0: control data cs (cif=1) figure 8. control i/f timing * read command is not supported. ? register map addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 0 0 pwvr pwad peda 01h reset control 0 0 0 0 0 0 rstad rstda 02h clock and format control dif2 dif1 dif0 cmode cks1 cks0 dfs1 dfs0 03h deem and volume control sm ute 0 0 zcei ztm1 ztm0 dem1 dem0 04h lch ipga control ipgl7 ipgl6 ipg l5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 05h rch ipga control ipgr7 ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 06h lch att control 0 attl6 a ttl5 attl4 attl3 a ttl2 attl1 attl0 07h rch att control 0 attr6 a ttr5 attr4 attr3 attr2 attr1 attr0 note: for addresses from 08h to 1fh, data is not written. pd = ?l? resets the registers to their default values.
[ak4524] m0050-e-04 2012/01 - 20 - ? control register setup sequence when pd pin goes ?l? to ?h? upon power-up etc., the ak4524 should operate by the next sequence. in this case, all control registers are set to initial values and the ak4524 is in the reset state. (1) set the clock mode and the audio data interface mode. (2) cancel the reset state by setting rstad or rstda to ?1?. refer to reset contorl register (01h). (3) adc outputs and dac output s should be muted externally until cancelling each reset state. in master mode, there is a possibility the frequency and duty of lrck and bick outputs become an abnormal state. the clock mode should be changed afte r setting rstad and rstda to ?0?. at that time, adc out puts and dac outputs should be muted externally. in master mode, there is a possibility the frequency and dut y of lrck and bick outputs become an abnormal state. ? register definitions addr register name d7 d6 d5 d4 d3 d2 d1 d0 00h power down control 0 0 0 0 0 pwvr pwad pwda reset 0 0 0 0 0 1 1 1 pwda: dac power down 0: power down 1: power up only dac section is powered down by ?0? and then the aouts go hi-z immediately. the oatts also go ?00h?. but the contents of all register are not initiali zed and enabled to write to the registers. after exiting the power down mode, the oatts fade in the setting value of the control register (06h & 07h). the analog outputs should be muted externally as some pop noise may occur when entering to and exiting from this mode. pwad: adc power down 0: power down 1: power up only adc section is powered down by ?0? and then the sdto goes ?l? immediately. the ipgas also go ?00h?. but the contents of all register are not initiali zed and enabled to write to the registers. after exiting the power down mode, the ipgas fade in the setting value of the control register (04h & 05h). at that time, adcs output ?0? during first 516 lrck cycles. pwvr: vref power down 0: power down 1: power up all sections are powered down by ?0? and then both adc and dac do not operate. the contents of all register are not initialized and enabled to write to the registers. when pwad and pwda go ?0? and pwvr goes ?1?, only vref section can be powered up.
[ak4524] m0050-e-04 2012/01 - 21 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 01h reset control 0 0 0 0 0 0 rstad rstda reset 0 0 0 0 0 0 0 0 rstda: dac reset 0: reset 1: normal operation the internal timing is reset by ?0? and then the aouts go vcom voltage i mmediately. the oatts also go ?00h?. but the contents of all register are not initialized and enabled to write to the registers. after exiting the power down mode, the oatts fade in the setting value of the control register (06h & 07h). the analog outputs should be muted externally as so me pop noise may occur when entering to and exiting from this mode. rstda: adc reset 0: reset 1: normal operation the internal timing is reset by ?0? and then sdto goes ?l? immediately. the ipgas also go ?00h?. but the contents of all register are not initialized and enabled to write to the register. after exiting the power down mode, the ipgas fade in the setting value of the control register (04h & 05h). at that time, adcs output ?0? during first 516 lrck cycles. addr register name d7 d6 d5 d4 d3 d2 d1 d0 02h clock and format control dif2 dif1 dif0 cmode cks1 cks0 dfs1 dfs0 reset 0 1 0 0 0 0 0 0 dfs1-0: sampling speed control (see table 2) initial: normal speed cmode, cks1-0: master clock frequency select (see table 1) initial: 256fs dif2-0: audio data interface modes (see table 4) 000: mode 0 001: mode 1 010: mode 2 011: mode 3 100: mode 4 initial: 24bit msb justified for both adc and dac
[ak4524] m0050-e-04 2012/01 - 22 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 03h deem and volume control sm ute 0 0 zcei ztm1 ztm0 dem1 dem0 reset 0 0 0 1 1 0 0 1 dem1-0: de-emphasis response (see table 7) 00: 44.1khz 01: off 10: 48khz 11: 32khz initial: off ztm1-0: zero crossing time out period select (see table 6) initial: 1024fs zcei: adc ipga zero crossing enable 0: input pga gain changes occur immediately 1: input pga gain changes occur only on zero-crossing or after timeout. initial: 1 (enable) smute: dac input soft mute control 0: normal operation 1: dac outputs soft-muted the soft mute is independent of the output att and performed digitally. addr register name d7 d6 d5 d4 d3 d2 d1 d0 04h lch ipga control ipgl7 ipgl6 i pgl5 ipgl4 ipgl3 ipgl2 ipgl1 ipgl0 05h rch ipga control ipgr7 ipgr6 ipgr5 ipgr4 ipgr3 ipgr2 ipgr1 ipgr0 reset 0 1 1 1 1 1 1 1 ipgl/r7-0: adc input gain level refer to table 10 initial: 7fh (0db) digital att with 128 levels operates when writing data of less than 7fh. this att is a linear att with 8032 levels internally and these levels are assigned to pseudo-log data with 128 levels. the transition between att values has 8032 levels and is done by so ft changes. for example, when att changes from 127 to 126, the internal att value decreases from 8031 to 7775 one by one every fs cycles. it takes 8031 cycles (182ms@fs=44.1khz) from 127 to 0 (mute). the ipgas are set to ?00h? when pd pin goes ?l?. after returning to ?h?, the ipgas fade in the initial value, ?7fh? by 8031 cycles. the ipgas are set to ?00h? when pwad goes ?0?. after returning to ?1?, the ipgas fade in the current value. but the adcs output ?0? during first 516 cycles. the ipags are set to ?00h? when rstad goes ?0?. afte r returning to ?1?, the ipgas fade in the current value. but the adcs output ?0? during first 516 cycles.
[ak4524] m0050-e-04 2012/01 - 23 - data internal (datt) gain (db) step width (db) 255 - 165 - +18 - 164 - +18 - 163 - +17.5 0.5 162 - +17 0.5 : - : 0.5 130 - +1.0 0.5 129 - +0.5 0.5 128 - 0 0.5 ipga analog volume with 0.5db step 127 8031 0 - 126 7775 ? 0.28 0.28 125 7519 ? 0.57 0.29 : : : : 112 4191 ? 5.65 0.51 111 3999 ? 6.06 0.41 110 3871 ? 6.34 0.28 : : : : 96 2079 ? 11.74 0.52 95 1983 ? 12.15 0.41 94 1919 ? 12.43 0.28 : : : : 80 1023 ? 17.90 0.53 79 975 ? 18.32 0.42 78 943 ? 18.61 0.29 : : : : 64 495 ? 24.20 0.54 63 471 ? 24.64 0.43 62 455 ? 24.94 0.30 : : : : 48 231 ? 30.82 0.58 47 219 ? 31.29 0.46 46 211 ? 31.61 0.32 : : : : 32 99 ? 38.18 0.67 31 93 ? 38.73 0.54 30 89 ? 39.11 0.38 : : : : 16 33 ? 47.73 0.99 15 30 ? 48.55 0.83 14 28 ? 49.15 0.60 : : : : 5 10 ? 58.10 1.58 4 8 ? 60.03 1.94 3 6 ? 62.53 2.50 2 4 ? 66.05 3.52 1 2 ? 72.07 6.02 0 0 mute iatt external 128 levels are converted to internal 8032 linear levels of datt. internal datt soft-changes between datas. datt=2^m x (2 x l + 33) ? 33 m: msb 3-bits of data l: lsb 4-bits of data table 10. ipga code table
[ak4524] m0050-e-04 2012/01 - 24 - addr register name d7 d6 d5 d4 d3 d2 d1 d0 06h lch oatt control 0 attl6 a ttl5 attl4 attl3 attl2 attl1 attl0 07h rch oatt control 0 attr6 a ttr5 attr4 attr3 attr2 attr1 attr0 reset 0 1 1 1 1 1 1 1 attl/r6-0: dac att level refer to table 11 initial: 7fh (0db) the ak4524 includes digital att with 128 levels equivalent to adc?s. the oatts are set to ?00h? when pd pin goes ?l?. after returning to ?h?, the oatts fade in the initial value, ?7fh? by 8031 cycles. the oatts are set to ?00h? when pwda goes ?0?. after returning to ?1?, the oatts fade in the current value. the oatts are set to ?00h? when rstda goes ?0?. afer returning to ?1?, the oatts fade in the current value. figure 9. att characteristics -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 127 111 95 79 63 47 31 15 input data(level) att(db) 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 step(db) step (db) att (db)
[ak4524] m0050-e-04 2012/01 - 25 - data internal (datt) gain (db) step width (db) 127 8031 0 - 126 7775 ? 0.28 0.28 125 7519 ? 0.57 0.29 : : : : 112 4191 ? 5.65 0.51 111 3999 ? 6.06 0.41 110 3871 ? 6.34 0.28 : : : : 96 2079 ? 11.74 0.52 95 1983 ? 12.15 0.41 94 1919 ? 12.43 0.28 : : : : 80 1023 ? 17.90 0.53 79 975 ? 18.32 0.42 78 943 ? 18.61 0.29 : : : : 64 495 ? 24.20 0.54 63 471 ? 24.64 0.43 62 455 ? 24.94 0.30 : : : : 48 231 ? 30.82 0.58 47 219 ? 31.29 0.46 46 211 ? 31.61 0.32 : : : : 32 99 ? 38.18 0.67 31 93 ? 38.73 0.54 30 89 ? 39.11 0.38 : : : : 16 33 ? 47.73 0.99 15 30 ? 48.55 0.83 14 28 ? 49.15 0.60 : : : : 5 10 ? 58.10 1.58 4 8 ? 60.03 1.94 3 6 ? 62.53 2.50 2 4 ? 66.05 3.52 1 2 ? 72.07 6.02 0 0 mute oatt external 128 levels are converted to internal 8032 linear levels of datt. internal datt soft-changes between datas. datt=2^m x (2 x l + 33) ? 33 m: msb 3-bits of data l: lsb 4-bits of data table 11. oatt code table
[ak4524] m0050-e-04 2012/01 - 26 - system design figure 10 & figure 11 show the system connection diagram. this is an example which the ak4524 operates at x?tal mode. in case of external clock mode, please refer to fi gure 11. an evaluation board (akd4524) is available which demonstrates application circuits, the optimum lay out, power supply arrangements and measurement results. + 4.75 5.25v a nalog supply 10u 10u 0.1u 0.1u 0.1u 0.1u 5 c c vd rch out lch out 2.7 5.25v digital supply mode setting a udio controller rch lpf lch lpf vcom a inr a inl vref a gnd va xto xti xtale lrck bick sdto sdti cdti cclk cs cif clko vt vd dgnd a outl- a outl+ a outr- a outr+ pd m/ s 1 2 3 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 a k4524 test + 10 22 23 4 notes: - x?tal oscillation circuit is specified from 11.2896mhz to 24.576mhz. - agnd and dgnd of ak4524 should be distributed separately from the ground of external controller etc. - when aout+/ ? drives some capacitive load, some resistor should be added in series between aout+/ ? and capacitive load. - all input pins except pull-down pin (test) should not be left floating. figure 10. typical connection diagram (x?tal mode) x?tal frequency c 11.2896mhz, 12.288mhz 33pf 16.384mhz, 16.9344mhz, 18.432mhz 15pf 22.5792mhz, 24.576mhz 10pf table 12. external capacitance example for x?tal (please contact x?tal oscillator manufacturer)
[ak4524] m0050-e-04 2012/01 - 27 - + 4.75 5.25v a nalog supply 10u 10u 0.1u 0.1u 0.1u 0.1u 5 rch out lch out 2.7 5.25v digital supply mode setting a udio controller rch lpf lch lpf vcom a inr a inl vref a gnd va xto xti xtale lrck bick sdto sdti cdti cclk cs cif clko vt vd dgnd a outl- a outl+ a outr- a outr+ pd m/ s 1 2 3 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 a k4524 test + 10 22 23 4 figure 11. typical connection diagram (ext clock mode) 1. grounding and power supply decoupling the ak4524 requires careful attention to power supply a nd grounding arrangements. va and vd are usually supplied from analog supply in system. alternatively if va and vd are supplied separately, the power up sequence is taken care. vt is a power supply pin to interface with the external ics and is supplie d from digital supply in system. agnd and dgnd of the ak4524 should be connected to analog ground plane. system analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. decoupling capacitors should be as near to the ak4524 as possible, with the small value ceramic capacitor being the nearest. 2. voltage reference the differential voltage between vref and agnd sets the an alog input/output range. vref pin is normally connected to va with a 0.1uf ceramic capacitor. vcom is a signal ground of this chip. an electrolytic capacitor 10uf parallel with a 0.1uf ceramic capacitor attach ed to vcom pin eliminates the effects of high frequency noise. no load current may be drawn from vcom pin. all signals, especially clocks, should be kept away from the vref and vcom pins in order to avoid unwanted coupling into the ak4524.
[ak4524] m0050-e-04 2012/01 - 28 - 3. analog inputs the ipga inputs are single-ended and the input resistance 5k (min). the input signal range scales with the vref voltage and nominally 0.58 x vref vpp centered in the inte rnal common voltage (about va/2). usually the input signal is ac coupled with capacitor. the cut-off frequency is fc = (1/2 rc). the ak4524 can accept input voltages from agnd to va. the adc output data format is 2?s compleme nt. the output code is 7fffffh (@24bit) for input above a positive full scale and 800000h(@24bit) for input below a nega tive fill scale. the ideal code is 000000h(@24bit) with no input signal. the dc offset including adc own dc offset removed by the internal hpf. the ak4524 samples the analog inputs at 64fs. the digital f ilter rejects noise above the stopband except for multiples of 64fs. the ak4524 includes an anti-aliasing filter (rc filter) to attenuate a noise around 64fs. 4. analog outputs the analog outputs are full differential outputs and nominally 0.54 x vref vpp centered in the internal common voltage (about va/2). the differential outputs are summed externally, vout = (aout+) ? (aout ? ) between aout+ and aout ? . if the summing gain is 1, the output range is 5.4vpp (typ@vref=5v). the bias voltage of the external summing circuit is supplied externally. the input data format is 2?s complement. the output voltage is a positive full scale for 7fffffh(@24bit) and a negative full scale for 800000h (@24bit). the ideal aout is 0v for 000000h(@24bit). the internal switched-capacitor filter and the external lpf attenuate the noise ge nerated by the delta-sigma modulator beyond the audio passband. differential outputs can eliminate any dc offset on analog outputs without using capacitors. figure 12 to figure 14 show the example of external op-amp circuit summing the differential outputs. a out- a out+ bias vop vop analog out 4.7k 4.7k r1 4.7k 3300p r1 4.7k 470p 470p 1k 1k 0.1u 47u when r1=200ohm fc=93.2khz, q=0.712, g=-0.1db at 40khz when r1=180ohm fc=98.2khz, q=0.681, g=-0.2db at 40khz + - + figure 12. external 2nd order lpf example (using single supply op-amp)
[ak4524] m0050-e-04 2012/01 - 29 - a out- a out+ +vop -vop analog out 4.7k 4.7k r1 4.7k 3300p r1 4.7k 470p 470p when r1=200ohm fc=93.2khz, q=0.712, g=-0.1db at 40khz when r1=180ohm fc=98.2khz, q=0.681, g=-0.2db at 40khz + - figure 13. external 2nd order lpf example (using dual supply op-amp) a out- a out+ +vop -vop analog out 4.7k 4.7k 4.7k 4.7k 180p 180p fc=188khz + - figure 14. external low cost 1st order lpf example (using dual supply op-amp) ? peripheral i/f example the digital inputs of the ak4524 are ttl inputs and can accept the signal of device with a nominal 3v supply. the digital output can interface with the pe ripheral device with a nominal 3v suppl y when the vt supply operates at a nominal 3v supply. 5v analog 3v digital 3 or 5v digital digital a nalog i/f a udio signal dsp up & others control signal ak4524 figure 15. power supply connection example
[ak4524] m0050-e-04 2012/01 - 30 - package 1.30 0.1 0.1 0-8 detail a seating plane note: dimension "*" does not include mold flash. 0.10 0.220.05 0.32 0.08 0.65 10.40max 2.1max a 1 14 15 28 28pin ssop (unit: mm) 5.30 7.90 0.20 0.60 0.15 ? package & lead frame material package molding compound: epoxy lead frame material: cu lead frame surface treatment: solder plate
[ak4524] m0050-e-04 2012/01 - 31 - marking AK4524VM xxxbyyyyc xxxbyyyyc: date code identifier xxxb: lot number (x: digit num ber, b: alpha character) yyyyc: assembly date (y: digit number, c: alpha character) date (y/m/d) revision reason page contents 98/12/05 00 first edition 99/05/25 01 error 19, 24 addr:07h, d5: attl5 attr5 correction 28 3. analog input, line 2: usually the signal input a 31 ?inportant notice? was added. 99/11/17 02 specification change 3, 5 ambient temperature: 10 a 70 q c o 20 a 85 q c error 10 timing diagram, clock timing correction mclk input level: 1.5v o vil, vih clko output level: vih, vil o 50%vt timing diagram, a udio interface timing (slave) sdto output level: vih, vil o 50%vt 11 timing diagram, a udio interface timing (master) lrck output level: vih, vil o 50%vt bick output level: vih, vil o 50%vt sdto output level: vih, vil o 50%vt description change 12, 13, 15 system clock table 1, 2, 3, 6 04/01/07 03 error correction 7 filter characteristics adc passband 22.20 o 20.20 12/01/12 04 specification change 1, 3, 30, 31 ak4524vf was deleted. (28pin vsop) AK4524VM was added. (28pin ssop) ordering guide was changed. package was changed. marking was changed. revision history
[ak4524] m0050-e-04 2012/01 - 32 - important notice z these products and their specifications are subject to change without notice. when you consider any use or application of these produc ts, please make inquiries the sales office of asahi kasei microdevices corporation (akm) or authorized distributors as to current status of the products. z descriptions of external circuits, application circuits, software and other related information contained in this document are provided only to illustrate the operation and application exampl es of the semiconductor products. you are fully responsible for the incorporation of these external circuits, application circuits, software and other related information in the design of your e quipments. akm assumes no responsibility fo r any losses incurred by you or third parties arising from the use of these information herein. akm assumes no liability for infringement of any patent, intellectual property, or other rights in the applica tion or use of such information contained herein. z any export of these products, or devices or systems containi ng them, may require an export license or other official approval under the law and regulations of the country of e xport pertaining to customs and tariffs, currency exchange, or strategic materials. z akm products are neither intended nor aut horized for use as critical components note1 ) in any safety, life support, or other hazard related device or system note2 ) , and akm assumes no responsibility fo r such use, except for the use approved with the express written consent by representative director of akm. as used here: note1 ) a critical component is one whose failure to functi on or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. note2 ) a hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aeros pace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. z it is the responsibility of the buyer or distributor of akm products , who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above conten t and conditions, and the buyer or distributor agrees to assume any and all responsib ility and liability for and hold akm harmless from any and all claims arising from the use of said product in the absence of such notification.

▲Up To Search▲

Price & Availability of AK4524VM

	To Download AK4524VM Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .